ALSEP Array E multilayer printed circuit board source qualification test plan

Romans, A. W.

dc.contributor.author	Romans, A. W.
dc.date.accessioned	2015-09-09T22:30:14Z
dc.date.available	2015-09-09T22:30:14Z
dc.date.issued	1971
dc.identifier.other	31111000670081
dc.identifier.uri	https://hdl.handle.net/20.500.11753/391
dc.description.abstract	This document provides a test plan for source or manufacturer qualification in the manufacture and supply of multilayer printed circuit system(s) with plated through holes.
dc.description.statementofresponsibility	prepared by A. W. Romans.
dc.format.extent	7 leaves
dc.format.mimetype	application/pdf
dc.language.iso	en
dc.publisher	Bendix Aerospace Systems Division
dc.relation.ispartofseries	ALSEP technical memorandum ; 988
dc.source.uri	https://www.lpi.usra.edu/lunar/ALSEP/pdf/31111000670081.pdf
dc.subject.lcc	TL789.8.U6A5
dc.subject.lcsh	Apollo Lunar Surface Experiments Package
dc.subject.lcsh	Printed circuits
dc.title	ALSEP Array E multilayer printed circuit board source qualification test plan
dc.title.alternative	Apollo Lunar Surface Experiments Package Array E multilayer printed circuit board source qualification test plan