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Analysis of LPTTL, its capabilities and deficiencies when used by itself or in interface with LPDTL

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dc.contributor.author Andreasen, K. D.
dc.date.accessioned 2015-09-09T22:27:09Z
dc.date.available 2015-09-09T22:27:09Z
dc.date.issued 1970
dc.identifier.other 31111000666451
dc.identifier.uri https://hdl.handle.net/20.500.11753/179
dc.description.abstract The purpose of this memo is to investigate the interface conditions arising from the use of low power transistor-transistor logic (LPTTL) in conjunction with low power diode-transistor logic (LPDTL) and to familiarize the reader with the fundamental characteristics which make transistor-transistor logic (TTL) of any power level unique, demonstrating the inherent performance characteristic limits of low power transistor-transistor logic if applied in conventional logic design.
dc.description.statementofresponsibility prepared by K. D. Andreasen.
dc.format.extent 15 leaves
dc.format.mimetype application/pdf
dc.language.iso en
dc.publisher Bendix Aerospace Systems Division
dc.relation.ispartofseries ALSEP technical memorandum
dc.source.uri https://www.lpi.usra.edu/lunar/ALSEP/pdf/ALSEP%20%23412%20-%20Analy_LPTTL_ATM%20916.pdf
dc.subject.lcc TL789.8.U6A5
dc.subject.lcsh Apollo Lunar Surface Experiments Package
dc.subject.lcsh Transistor-transistor logic circuits
dc.title Analysis of LPTTL, its capabilities and deficiencies when used by itself or in interface with LPDTL
dc.title.alternative Analysis of low power transistor-transistor logic, its capabilities and deficiencies when used by itself or in interface with low power diode-transistor logic


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    Apollo Lunar Surface Experiment Package (ALSEP) Documents

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